Particular embodiments generally relate to sampling circuits, and more particularly to analog-to-digital converters (ADC).
Unless otherwise indicated herein, the approaches described in this section are not admitted to be prior art by inclusion in this section.
A successive approximation register (SAR) analog-to-digital converter (ADC) may convert an analog signal to a digital signal using a binary search algorithm in a feedback loop. The SAR ADC samples an input signal every clock cycle during a sampling phase on the top or bottom plates of the digital-to-analog converter (DAC) capacitors. The top plate is defined as the capacitor terminal that connects to the comparator inputs during the conversion phase described later. For example, in a top plate sampling scheme, the input signal is sampled on the top plate of the DAC capacitor array during the sampling phase. A digital controller resets a comparator and bottom plates of the DAC capacitors. In this example, the top half of the DAC are reset to a reference +ref and the bottom half of the DAC is reset to a reference −ref. The sampling phase then samples the input signal on the top plates of the DAC capacitors.
A conversion phase follows every sampling phase. In the conversion phase, the sampled input signal is input into the comparator. In the SAR ADC, the conversion is performed from a most significant bit (MSB) to the least significant bit (LSB). The digital controller enables and initiates a comparator decision for each conversion phase. The comparator output then drives the controller. Once the comparator has performed the comparison, the MSB output decision is registered as a “0” or “1” based on the comparator decision. The controller then advances to the next bit, and initiates the next comparator decision using the input signal. The above process continues until all bits have been resolved.
When a single-ended input is used, a comparator common mode varies as the decision process proceeds to resolve the bits of the digital signal. The common mode of the comparator is the average voltage at the comparator input. The common mode of the comparator varies because a second input of the comparator is typically coupled to ground when using the single-ended input. In this case, the common mode of the comparator varies because the second input (e.g., the comparator negative input) is constant while the input signal varies on the first input (e.g., the comparator positive input). From the most significant bit to the least significant bit, the common mode of the comparator varies. The varying common mode may make it hard to design a high-speed comparator.
To avoid the varying of the common mode of the comparator, a differential SAR ADC design may use a differential input, differential DACs, and a differential comparator. The input signal includes two inputs vin+ and vin−, with half the input signal on each side of the differential comparator. Each half input signal may be sampled as the input to the differential DACs. The comparator decisions and output codes are the same as with the single-ended input. However, the differential input seen by the comparator is constant throughout the conversion, and thus the comparator common mode remains constant.